both apple m cpus and snapdragon have hardware magic to make translation viable when paired with usermode tools like Rozetta or Prism
otherwise it’s painfully slow, as demonstrated by both box64 and fex.
well apple cpus have a hardware flag which slightly changes side effects of some existing arm instructions AND completely changes the memory model to one that imitates Intel x86 for the current thread. (TSO)
with this flag enabled, the code can be almost fully recompiled ahead-of-time (from x86_64 to arm64) with minimal overhead (no need to remap memory addresses etc), with no reason to resort to e.g. jit recompilation on the fly (which is exactly what box64 does all the time)
i assume snapdragon and microsoft are doing a similar thing (it definitely involves some hw magic too, maybe not exactly the same as in apple) since it’s seemingly the only way to achieve parity with apple in terms of performance
not hw accelerated
I’m not sure that means anything. For it to be hardware accelerated you would need a amd64 cpu
both apple m cpus and snapdragon have hardware magic to make translation viable when paired with usermode tools like Rozetta or Prism
otherwise it’s painfully slow, as demonstrated by both box64 and fex.
Do you have a source for that? It seems like that would defeat the purpose of using ARM.
well apple cpus have a hardware flag which slightly changes side effects of some existing arm instructions AND completely changes the memory model to one that imitates Intel x86 for the current thread. (TSO)
with this flag enabled, the code can be almost fully recompiled ahead-of-time (from x86_64 to arm64) with minimal overhead (no need to remap memory addresses etc), with no reason to resort to e.g. jit recompilation on the fly (which is exactly what box64 does all the time)
i assume snapdragon and microsoft are doing a similar thing (it definitely involves some hw magic too, maybe not exactly the same as in apple) since it’s seemingly the only way to achieve parity with apple in terms of performance